1. Field of the Invention
The present invention generally relates to a timing generation device that generates a timing signal from a signal received via a transmission line. More particularly, the present invention is concerned with a timing generation device suitable for a data transmission device which demodulates a received signal transmitted via a high-bit-rate main (primary) channel and a low-bit-rate secondary channel having a frequency band different from that of the high-bit-rate main channel.
2. Description of the Prior Art
A data transmission device, such as a modem (modulator and demodulator), regenerates a transmission tinning signal from a signal received via a transmission line. The transmission timing signal is used to reproduce the original transmission signal from the received signal.
Recently, it has been required that data be transmitted via an analog transmission line having the voice band at a high transmission speed (bit rate). As the transmission speed increases, it becomes difficult to extract a timing component from the received signal. Hence, it is desired to easily extract the timing component from the signal received via the analog transmission line at a high transmission speed.
As shown in FIG. 1A, a signal transmitted via an analog transmission line has a main (primary) channel and a secondary channel which are arranged in the voice band between 0.3 kHz and 3.4 kHz. The main channel has a frequency band of 3000 Hz, and the secondary channel has a frequency band of 100 Hz. Main data modulated by a QAM (Quadrature Amplitude Modulation) process at a transmission speed of 9600 bps is transmitted via the main channel. Control data used to manage the network is modulated by a FSK (Frequency Shift Keying) process and transmitted via the secondary channel. For example, control data necessary to notify a host communications device of the status of the modem or to test the network is transmitted via the secondary channel. The control data is transmitted at a transmission speed of, for example, 50 bps.
FIG. 1B is a block diagram of a receiver of a modem which handles a signal transmitted via the main and secondary channels (see Japanese Laid-Open Patent Publication No. 61-82545). An analog signal received via an analog transmission line (not shown) is applied to a low-pass filter (LPF) 40, which eliminates high-frequency components therefrom. The analog signal from the low-pass filter 40 is applied to an A/D (Analog-to-Digital) converter 41. A digital signal generated from the A/D converter 41 is applied to a processor 1, such as a digital signal processor (DSP).
The processor 1 is made up of a main channel system 2 and a secondary channel system 3. In the main channel system 2, the digital signal from the A/D converter 41 is demodulated by a demodulator (DEM) 20. A roll-off filter (ROF) 21 eliminates high-frequency components from the demodulated signal, and shapes the waveform of the demodulated signal. An equalizer (EQL) 22 equalizes the waveform of the output signal of the roll-off filter 21. A carrier phase controller (ACPC) 23 eliminates jitter from the equalized signal from the equalizer 22. A decision unit (DEC) 24 identifies data transmitted via the main channel from the output signal of the carrier phase controller 23.
The output signal of the roll-off filter 21 is applied to a timing extractor (TIM) 25, which extracts a timing component from the output signal of the roll-off filter 21. A primary integration circuit 26, which is made up of a delay element having a unit delay time T and two adders, executes a frequency integration operation on the output signal of the timing extractor 25 in order to stabilize the frequency components affected by the jitter. A secondary integration circuit 27, which is made up of a delay element having the unit delay time T and an adder, executes a phase integration operation on the output signal of the primary integration circuit 26 in order to stabilize a phase error signal component contained in the output signal of the primary integration circuit 26. A decision unit (DEC) 28 identifies phase error and outputs a phase error signal to a 1/n counter 29. The frequency dividing ratio of the 1/n counter 29 is changed in accordance with the phase error signal. That is, the structural elements 26-29 form a phase-locked loop (PLL) circuit. The output signal of the 1n counter 29 is applied, as an internal timing signal, to the A/D converter 41, which uses the internal timing signal as a sampling clock signal.
In the secondary channel system 3, a demodulator (DEM) 30 demodulates the digital signal from the A/D converter 41. A roll-off filter (ROF) 31 eliminates high-frequency components from the demodulated signal from the demodulator 30, and shapes the waveform thereof. An equalizer (EQL) 32 equalizes the waveform of the output signal of the roll-off filter 31. A carrier phase controller (ACPC) 33 eliminates jitter from the equalized signal from the equalizer 32. A decision unit (DEC) 34 identifies data transmitted via the secondary channel from the output signal of the carrier phase controller 33.
In practice, the above-mentioned structural elements of the processor 1 correspond to processes executed by the processor 1.
However, the conventional device shown in FIG. 1B has the following disadvantages. As shown in FIG. 2A, when the roll-off rate of the roll-off filter 21 is high (100% in FIG. 2A), the transmission speed is slow and is, for example, 1000 bauds. However, in this case, timing extraction can be easily performed. The roll-off rate of the roll-off filter 21 is defined as shown in FIG. 2C.
When the transmission speed of the main channel is increased to 2000 bauds in order to satisfy the recent requirement of high bit-rate data transmission, it is necessary to reduce the roll-off rate as shown in FIG. 2B in order to transfer data via the main channel in the voice band. In the case shown in FIG. 2B, it is very difficult to extract the timing component from the signal transmitted via the main channel because the timing component is extracted from energy existing in areas indicated by hatching in FIG. 2B. That is, extraction of the timing component becomes difficult as the transmission speed of the main channel increases. In the case shown in FIG. 2B, the PLL circuit does not accurately operate, and the transmission device erroneously may reproduce the original transmission data.